Did AI chip designs consolidate after the V100?
Exploring whether frontier AI training shifted from spreading across diverse chip designs to concentrating on fewer, heavily-reused architectures around the time of NVIDIA's V100 release.
The same Epoch AI analysis (Luke Emberson, Ben Snodin, David Owen, 2025-03-05) finds that frontier AI training concentrated onto far fewer chip designs once the NVIDIA V100 arrived. Across its dataset of 149 frontier AI models, "pre-V100 chip designs trained an average of only 2.1 frontier models each, compared to an average of 9.3 frontier models per chip among V100 and newer designs." Epoch AI reads this as a shift "towards large-scale industrial AI training runs," noting that before the V100, "frontier AI training was spread across a wider variety of chip designs."
The comparison comes from the same join of Epoch AI's Notable Models and Machine Learning Hardware datasets used to compute chip lifespan, counting how many of the 149 identified frontier-model training runs used each of the 14 chip designs. A separate check against the broader Notable Models dataset — not restricted to the top-10-by-compute "frontier" tier — finds a lower median lifespan of 2.1 years across 9 V100-and-newer chip designs, because non-frontier "notable" training spreads across many more chip designs, and "most of the chips that were unseen among frontier models are significantly less popular, and consequently tend to have shorter lifespans." The contrast between the two figures is itself evidence for the consolidation claim: frontier-scale training clusters on fewer, longer-lived designs than AI training in general.
This is the mechanism behind the lifespan figure in How long do leading AI chips stay in frontier training?: a chip design's frontier lifespan can only stretch to 3.9 years if it keeps getting reused across successive frontier training runs rather than being replaced each generation, and the 9.3-models-per-chip average is the count of that reuse. It shares the same frontier-training-compute lens as Does pretraining loss predict performance after reinforcement learning?, though measuring hardware reuse across model generations rather than how a single training run should split compute between pretraining and RL.
The 9.3-versus-2.1 comparison averages over only 5 post-V100 and 7 pre-V100 chip designs, a sample small enough that one unusually long-lived or short-lived design shifts the average substantially; Epoch AI does not identify why the consolidation happened, only that it did. The excerpt does not establish whether the trend will continue as more AI-specific chip architectures (additional TPU generations, custom ASICs from other vendors) reach frontier scale — more competing designs could either extend the pattern or fragment it back toward the pre-V100 spread. What it does support is that frontier training since the V100 has relied on a narrower set of chip generations, each carrying more of the field's largest training runs than earlier hardware did.
Inquiring lines that read this note 10
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What cost drivers and infrastructure choices characterize frontier AI training?- Why did frontier training concentrate onto fewer chip designs after the V100?
- Do custom ASICs and new TPU generations extend chip lifespan beyond four years?
- How long do leading AI chip designs stay in use for frontier training?
- What drives consolidation of frontier training onto specific hardware vendors?
- Did non-frontier AI training spread across more chip designs than frontier training?
- Why did frontier training consolidate around specific chip designs after V100?
- Will custom ASICs and new architectures reverse the chip design consolidation trend?
- How much of frontier AI cost growth comes from chips versus skilled staff?
- Which spending categories drive the rising cost of frontier AI training?
- How much of frontier AI training costs come from staff versus hardware?
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How long do leading AI chips stay in frontier training?
Frontier AI training depends on specialized hardware. Understanding how long chips remain competitive for the largest training runs matters for hardware amortization planning and predicting when designs become obsolete.
the lifespan figure this chip-design concentration produces
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Does pretraining loss predict performance after reinforcement learning?
Can we predict how well a language model will perform after RL training based only on its pretraining loss? Understanding this connection could guide how to allocate compute between pretraining and RL stages.
shares the frontier-training-compute lens, measuring hardware reuse rather than the pretraining-to-RL split
Related papers in this collection 8
Papers most semantically related to this note, ranked by cosine similarity in the embedding space.
- Leading AI chip designs are used for around four years in frontier training
- PostTrainBench: Can LLM Agents Automate LLM Post-Training?
- The rising costs of training frontier AI models
- AI Compute Architecture and Evolution Trends
- Research note: Evidence on AI R&D Progress from NanoGPT
- Continual Learning Bench: Evaluating Frontier AI Systems in Real-World Stateful Environments
- The plunging price of thought
- The Price of Progress: Price Performance and the Future of AI
Original note title
Epoch AI finds AI chip designs since the NVIDIA V100 trained 9.3 frontier models on average versus 2.1 before it